Semiconductor device and method of manufacturing the same

ABSTRACT

In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device includes one or more interconnects insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior U.S. Provisional Patent Application No. 62/079,305 filed on Nov. 13, 2014, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device and a method of manufacturing the same.

BACKGROUND

In recent years, fine patterns of a semiconductor device are often formed by sidewall transfer process. For example, word lines of a semiconductor storage device such as a NAND memory are formed by the sidewall transfer process for downscaling purposes in many cases. However, when the word lines are formed by the sidewall transfer process, the reduction of the line width and the space width of the word lines makes it difficult to form pad portions (hook-up portions), which are used to dispose contact plugs on the word lines. The reason is that the reduction of these widths makes it difficult, when lithography for processing the pad portions is performed, to perform the alignment in lithography for dividing the pad portions and cutting the word lines from the pad portions. Therefore, a method that can process the pad portions simply and accurately is demanded.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 10B are plan views and cross-sectional views showing a method of manufacturing a semiconductor device of a first embodiment;

FIG. 11 is a graph showing a relation of an initial space width between patterns of an upper layer and a final space width between patterns of a lower layer, when the patterns of the upper layer are transferred to the lower layer;

FIGS. 12 and 13 are plan views showing a method of manufacturing a semiconductor device of a second embodiment;

FIG. 14 is a plan view showing a method of manufacturing a semiconductor device of a modification of the second embodiment; and

FIGS. 15 to 20 are plan views showing a method of manufacturing a semiconductor device of a third embodiment.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings.

In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate so as to be adjacent to one another. The device further includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device further includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction perpendicular to the first direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device further includes one or more interconnects electrically insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.

First Embodiment

FIGS. 1A to 10B are plan views and cross-sectional views showing a method of manufacturing a semiconductor device of a first embodiment. The semiconductor device of the present embodiment is a NAND memory.

FIG. 1A is a plan view showing the semiconductor device of the present embodiment. FIG. 1B is a cross-sectional view taken along line I-I′ in FIG. 1A. The same goes for FIGS. 2A to 10B.

[FIGS. 1A and 1B]

First, a gate insulator 2, a floating gate material 3, an inter gate insulator 4, a control gate material 5 that is an example of the interconnect layer, a first mask layer 11, a second mask layer 12, a hard mask layer 13 that is an example of the first film, a first core material 14 that is an example of the second film, a second core material 15 that is an example of the third film, and a resist film 16 are formed in order, on a substrate 1 (FIGS. 1A and 1B).

Examples of the substrate 1 include a semiconductor substrate such as a silicon substrate. FIGS. 1A and 1B show an X direction and Y direction that are parallel to the surface of the substrate 1 and that are perpendicular to each other, and show a Z direction that are perpendicular to the surface of the substrate 1. The X direction and the Y direction are examples of the first direction and the second direction, respectively.

In this specification, the +Z direction is handled as the upward direction, and the −Z direction is handled as the downward direction. For example, the positional relation between the substrate 1 and the resist film 16 is described as the substrate 1 being positioned below the resist film 16. The −Z direction in the present embodiment may agree with the gravity direction, or may disagree with the gravity direction.

Examples of the gate insulator 2 include a silicon oxide film. Examples of the floating gate material 3 include a polysilicon layer. Examples of the inter gate insulator 4 include a silicon oxide film, a silicon nitride film, and a laminated film including them. Examples of the control gate material 5 include a polysilicon layer, a metal layer, and a laminated film including them.

Examples of the first mask layer 11 include an insulator such as a silicon nitride film. Examples of the second mask layer 12 include a silicon oxide film. Examples of the hard mask layer 13 include a polysilicon layer and an amorphous silicon layer. Examples of the first core material 14 include a silicon oxide film. Examples of the second core material 15 include a silicon nitride film.

Next, the resist film 16 is processed by lithography (FIGS. 1A and 1B). As a result, the resist film 16 is processed into a resist pattern including belt portions 16A, 16B and line portions 16C, 16D.

The belt portions 16A, 16B extend in the X direction, and surround opening portions P_(A), P_(B), respectively. The line portions 16C, 16D extend mainly in the Y direction, and are connected with the belt portions 16A, 16B, respectively. The opening portions P_(A), P_(B) are positioned near end portions of the line portions 16C, 16D, respectively.

The resist pattern further includes multiple belt portions having the same shape as the belt portions 16A, 16B, and multiple line portions having the same shape as the line portions 16C, 16D, but the illustration of these is omitted in FIGS. 1A and 1B. The same goes for the other patterns shown in FIGS. 2A to 10B.

[FIGS. 2A and 2B]

Next, by the etching using the resist film 16 as a mask, the second core material. 15 is processed (FIGS. 2A and 2B). As a result, the second core material 15 is processed into a core material pattern including belt portions 15A, 15B and line portions 15C, 15D. The core material pattern of the second core material 15 is an example of the first pattern. Further, examples of the above etching include a reactive ion etching (RIE).

The belt portions 15A, 15B extend in the X direction, and surround opening portions Q_(A), Q_(B), respectively. The line portions 15C, 15D extend mainly in the Y direction, and are connected with the belt portions 15A, 15B, respectively. The opening portions Q_(A), Q_(B) are positioned near end portions of the line portions 15C, 15D, respectively.

[FIGS. 3A and 3B]

Next, a first sidewall film 17 is formed on the side faces of the second core material 15 (FIGS. 3A and 3B). Examples of the first sidewall film 17 include a silicon oxide film.

The first sidewall film 17 includes line portions 17C₁, 17C₂ formed on the side faces of the belt portion 15A and line portion 15C of the second core material 15, and line portions 17D₁, 17D₂ formed on the side faces of the belt portion 15B and line portion 15D of the second core material 15.

The first sidewall film 17 further includes a dummy portion 17E formed on the side faces of the opening portion Q_(A), and a dummy portion 17F formed on the side faces of the opening portion Q_(B). The dummy portions 17E, 17F have a ring shape.

[FIGS. 4A and 4B]

Next, the second core material 15 is removed by etching or ashing (FIGS. 4A and 4B).

[FIGS. 5A and 5B]

Next, by the etching using the first sidewall film 17 as a mask, the first core material 14 is processed (FIGS. 5A and 5B). As a result, the first core material 14 is processed into a core material pattern including belt portions 14A, 14B, line portions 14C₁, 14C₂, 14D₁, 14D₂, and dummy portions 14E, 14F. The core material pattern of the first core material 14 is an example of the second pattern. Further, examples of the above etching include an RIE. The dummy portions 14E, 14F, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the dummy portions 17E, 17F, respectively.

The belt portions 14A, 14B extend in the X direction. The line portions 14C₁, 14C₂, 14D₁, 14D₂ extend mainly in the Y direction. The line portions 14C₁, 14C₂ are connected with the belt portion 14A, and the line portions 14D₁, 14D₂ are connected with the belt portion 14B.

The dummy portion 17E is separated from the belt portion 14A and the line portions 14C₁, 14C₂, and is positioned between the line portion 14C₁ and the line portion 14C₂. The dummy portion 17E is adjacent to the belt portion 14A in the X direction. The line portions 14C₁, 14C₂ are examples of the first and second line portions, respectively, and the dummy portion 17E is an example of the portion that is positioned between the first line portion and the second line portion.

The dummy portion 17F is separated from the belt portion 14B and the line portions 14D₁, 14D₂, and is positioned between the line portion 14D₁ and the line portion 14D₂. The dummy portion 17F is adjacent to the belt portion 14B in the X direction. The line portions 14D₁, 14D₂ are examples of the first and second line portions, respectively, and the dummy portion 17F is an example of the portion that is positioned between the first line portion and the second line portion.

The line portions 17C₁, 17C₂, 17D₁, 17D₂ and dummy portions 17E, 17F of the first sidewall film 17 are transferred to the first core material 14, and thereby, the line portions 14C₁, 14C₂, 14D₁, 14D₂ and dummy portions 14E, 14F in the present embodiment are formed.

On the other hand, the belt portions 14A, 14B in the present embodiment are formed by the reverse loading effect. The reverse loading effect accelerates the etching rate for narrow space patterns, and decelerates the etching rate for wide space patterns. The reason is that the narrow space patterns are largely affected by the etching, compared to the wide space patterns.

In the present embodiment, the space between the line portions 17C₁, 17C₂ is wide at a region in the +X direction from the dummy portion 17E. Therefore, in the steps of FIGS. 5A and 5B, the first core material 14 at this region remains, and the belt portion 14A is formed.

Similarly, the space between the line portions 17D₁, 17D₂ is wide at a region in the +X direction from the dummy portion 17F. Therefore, in the steps of FIGS. 5A and 5B, the first core material 14 at this region remains, and the belt portion 14B is formed.

[FIGS. 6A and 6B]

Next, a second sidewall film 18 is formed on the side faces of the first core material 14 (FIGS. 6A and 6B). Examples of the second sidewall film 18 include a silicon nitride film.

The second sidewall film 18 includes line portions 18C₁ to 18C₄ formed on the side faces of the belt portion 14A and line portions 14C₁, 14C₂ of the first core material 14, and line portions 18D₁ to 18D₄ formed on the side faces of the belt portion 14B and line portions 14D₁, 14D₂ of the first core material 14.

The second sidewall film 18 further includes dummy portions 18E₁, 18E₂ formed on the side faces of the dummy portion 14E, and dummy portions 18F₁, 18F₂ formed on the side faces of the dummy portion 14F. The dummy portions 18E₁, 18F₁ have a ring shape, and the dummy portions 18E₂, 18F₂ have a line shape.

The line portions 18C₂, 18C₃ are connected with each other at a region between the belt portion 14A and the dummy portion 14E. Further, the line portions 18D₂, 18D₃ are connected with each other at a region between the belt portion 14B and the dummy portion 14F.

[FIGS. 7A and 7B]

Next, the first core material 14 is removed by etching or ashing (FIGS. 7A and 7B).

[FIGS. 8A and 8B]

Next, by the etching using the second sidewall film 18 as a mask, the hard mask layer 13 is processed (FIGS. 8A and 8B). As a result, the hard mask layer 13 is processed into a hard mask pattern including belt portions 13A, 13B, line portions 13C₁ to 13C₄, 13D₁ to 13D₄ and dummy portions 13E₁, 13E₂, 13F₁, 13F₂. The hard mask pattern is an example of the third pattern. Further, examples of the above etching include an RIE. The dummy portions 13E₁, 13E₂, 13F₁, 13F₂, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the dummy portions 18E₁, 18E₂, 18F₁, 18F₂, respectively.

The belt portions 13A, 13B extend in the X direction. The line portions 13C₁ to 13C₄, 13D₁ to 13D₄ extend mainly in the Y direction. The line portions 13C₁ to 13C₄ are connected with the belt portion 13A, and the line portions 13D₁ to 13D₄ are connected with the belt portion 13B.

The dummy portions 13E₁, 13E₂ are separated from the belt portion 13A and the line portions 13C₁ to 13C₄, and are positioned between the line portions 13C₁, 13C₂ and the line portions 13C₃, 13C₄. The dummy portions 13E₁, 13E₂ are adjacent to the belt portion 13A in the X direction. The line portions 13C₁ to 13C₄ are examples of the first to fourth line portions, respectively, and the dummy portions 13E₁, 13E₂ are examples of the portion that is positioned between the first and second line portions and the third and fourth line portions.

The dummy portions 13F₁, 13F₂ are separated from the belt portion 13B and the line portions 13D₁ to 13D₄, and are positioned between the line portions 13D₁, 13D₂ and the line portions 13D₃, 13D₄. The dummy portions 13F₁, 13F₂ are adjacent to the belt portion 13B in the X direction. The line portions 13D₁ to 13D₄ are examples of the first to fourth line portions, respectively, and the dummy portions 13F₁, 13F₂ are examples of the portion that is positioned between the first and second line portions and the third and fourth line portions.

The line portions 18C₁ to 18C₄, 18D₁ to 18D₄ and dummy portions 18E₁, 18E₂, 18F₁, 18F₂ of the second sidewall film 18 are transferred to the hard mask layer 13, and thereby, the line portions 13C₁ to 13C₄, 13D₁ to 13D₄ and dummy portions 13E₁, 13E₂, 13F₁, 13F₂ in the present embodiment are formed.

On the other hand, the belt portions 13A, 13B in the present embodiment are formed by the reverse loading effect. The reverse loading effect accelerates the etching rate for narrow space patterns, and decelerates the etching rate for wide space patterns. The reason is that the narrow space patterns are largely affected by etching, compared to the wide space patterns.

In the present embodiment, the space between the line portions 18C₁, 18C₄ is wide at a region in the +X direction from the connecting portion between the line portions 18C₂, 18C₃. Therefore, in the steps of FIGS. 8A and 8B, the hard mask layer 13 at this region remains, and the belt portion 13A is formed. However, the belt portion 13A is formed such that opening portions R_(A1), R_(A2) remain at corner portions of the belt portion 13 k The reason is that the distance between the line portions 18C₁, 18C₂ and the distance between the line portions 18C₃, 18C₄ are short near the corner portions.

Similarly, the space between the line portions 18D₁, 18D₄ is wide at a region in the +X direction from the connecting portion between the line portions 18D₂, 18D₃. Therefore, in the steps of FIGS. 8A and 8B, the hard mask layer 13 at this region remains, and the belt portion 13B is formed. However, the belt portion 13B is formed such that opening portions R_(B1), R_(B2) remain at corner portions of the belt portion 13B. The reason is the same as the case of the belt portion 13A.

[FIGS. 9A and 9B]

Next, by the etching using the hard mask layer 13 as a mask, the second mask layer 12, the first mask layer 11, the control gate material 5, the inter gate insulator 4, the floating gate material 3, and the gate insulator 2 are processed (FIGS. 9A and 9B). As a result, the first mask layer 11 is processed into a mask pattern including belt portions 11A, 11B, line portions 11C₁ to 11C₄, 11D₁ to 11D₄ and dummy portions 11E₁, 11E₂, 11F₁, 11F₂. Examples of the above etching include an RIE.

The same goes for the control gate material 5, the inter gate insulator 4, the floating gate material 3, and the gate insulator 2. For example, the control gate material 5 is processed into an interconnect pattern including belt portions 5A, 5B, line portions 5C₁ to 5C₄, 5D₁ to 5D₄, and dummy portions 5E₁, 5E₂, 5F₁, 5F₂.

The belt portions 5A, 5B, the line portions 5C₁ to 5C₄, 5D₁ to 5D₄, and the dummy portions 5E₁, 5E₂, 5F₁, 5F₂, for which the illustration of the reference characters and the shapes is omitted for the convenience of the figure drawing, are positioned under the belt portions 11A, 11B, the line portions 11C₁ to 11C₄, 11D₁ to 11D₄ and the dummy portions 11E₁, 11E₂, 11F₁, 11F₂, respectively. The line portions 5C₁ to 5C₄, 5D₁ to 5D₄ function as word lines WL₁ to WL₈, respectively.

The belt portions 11A, 11B extend in the X direction. The line portions 11C₁ to 11C₄, 11D₁ to 11D₄ extend mainly in the Y direction, and are arranged so as to be adjacent to each other. The line portions 11C₁ to 11C₄ are connected with the belt portion 11A, and the line portions 11D₁ to 11D₄ are connected with the belt portion 11B. The same goes for the belt portions 5A, 5B, and the line portions 5C₁ to 5C₄, 5D₁ to 5D₄.

The dummy portions 11E₁, 11E₂ are separated from the belt portion 11A and the line portions 11C₁ to 11C₄, and are positioned between the line portions 11C₁, 11C₂ and the line portions 11C₃, 11C₄. The dummy portions 11E₁, 11E₂ are adjacent to the belt portion 11A in the X direction. The dummy portion 11E₁ has a ring shape, and the dummy portion 11E₂ has a line shape. The same goes for the line portions 5C₁ to 5C₄ and the dummy portions 5E₁, 5E₂. The line portions 5C₁ to 5C₄ are examples of the first to fourth interconnects, respectively. The dummy portions 5E₁, 5E₂ are examples of the one or more interconnects. The dummy portions 5E₁, 5E₂ are separated (electrically insulated) from the belt portion 5A and the line portions 5C₁ to 5C₄.

The dummy portions 11F₁, 11F₂ are separated from the belt portion 11B and the line portions 11D₁ to 11D₄, and are positioned between the line portions 11D₁, 11D₂ and the line portions 11D₃, 11D₄. The dummy portions 11F₁, 11F₂ are adjacent to the belt portion 11B in the X direction. The dummy portion 11F₁ has a ring shape, and the dummy portion 11F₂ has a line shape. The same goes for the line portions 5D₁ to 5D₄ and the dummy portions 5F₁, 5F₂. The line portions 5D₁ to 5D₄ are examples of the first to fourth interconnects, respectively. The dummy portions 5F₁, 5F₂ are examples of the one or more interconnects. The dummy portions 5F₁, 5F₂ are separated (electrically insulated) from the belt portion 5B and the line portions 5D₁ to 5D₄.

Similarly to the belt portion 13A, the belt portion 11A in the present embodiment is formed such that opening portions S_(A1), S_(A2) remain at corner portions of the belt portion 11A. Reference characters K₁ to K₄ denote end portions of the line portions 11C₁ to 11C₄, respectively. The line portions 11C₁ to 11C₄ are connected with the belt portion 11A at the end portions K₁ to K₄, respectively. The same goes for the belt portion 11B and the line portions 11D₁ to 11D₄. Furthermore, the same goes for the belt portions 5A, 5B and the line portions 5C₁ to 5C₄, 5D₁ to 5D₄.

In the present embodiment, due to the opening portion S_(A1), the distance between the end portion K₁ of the line portion 11C₁ and the end portion K₂ of the line portion 11C₂ is greater than the space width between the line portion 11C₁ and the line portion 11C₂. Furthermore, due to the opening portion S_(A2), the distance between the end portion K₃ of the line portion 11C₃ and the end portion K₄ of the line portion 11C₄ is greater than the space width between the line portion 11C₃ and the line portion 11C₄. The same goes for the line portions 11D₁ to 11D₄. Furthermore, the same goes for the line portions 5C₁ to 5C₄, 5D₁ to 5D₄.

The space width between the line portion 11C₁ and the line portion 11C₂, and the space width between the line portion 11C₃ and the line portion 11C₄ are specified by the major portions of these line portions 11C₁ to 11C₄, that is, by the portions where these line portions 11C₁ to 11C₄ extend in the Y direction. Therefore, these space widths are roughly equal to the line widths of the line portions 17C₁, 17C₂ of the first sidewall film 17, and the line widths of the line portions 14C₁, 14C₂ of the first core material 14.

[FIGS. 10A and 10B]

Next, the belt portions 11A, 11B are divided by lithography and etching (FIGS. 10A and 10B). The same goes for the control gate material 5, the inter gate insulator 4, the floating gate material 3 and the gate insulator 2. Examples of the above etching include an RIE.

The belt portion 11A is divided by trenches T_(A), T_(A1), T_(A2). The trench T_(A) extends in the X direction such that the belt portion 11A is divided into two. The trench T_(A1) extends in the X direction and the Y direction such that the trench T_(A) and the opening portion S_(A1) are linked. The trench T_(A2) extends in the X direction and the Y direction such that the trench T_(A) and the opening portion S_(A2) are linked.

As a result, the belt portion 11A is divided into belt portions 11A₁ to 11A₄ that are connected with the line portions 11C₁ to 11C₄, respectively. The belt portions 11A₁, 11A₂ are adjacent to each other in the X direction, and the belt portions 11A₃, 11A₄ are adjacent to each other in the X direction. Further, the belt portions 11A₁, 11A₄ are adjacent to each other in the Y direction, and the belt portions 11A₂, 11A₃ are adjacent to each other in the Y direction.

In the present embodiment, a part of the belt portion 11A₁ is positioned in the +Y direction from the belt portion 11A₂, and a part of the belt portion 11A₄ is positioned in the −Y direction from the belt portion 11A₃. Therefore, the belt portions 11A₁, 11A₂ are adjacent to each other in the Y direction. Similarly, the belt portions 11A₃, 11A₄ are adjacent to each other in the Y direction.

Similarly to the belt portion 11A, the belt portion 5A is divided into belt portions 5A₁ to 5A₄ that are connected with the line portions 5C₁ to 5C₄, respectively. While the line portions 5C₁ to 5C₄ function as the word lines WL₁ to WL₄, respectively, the belt portions 5A₁ to 5A₄ function as pad portions (hook-up portions) HU₁ to HU₄ for the word lines WL₁ to WL₄, respectively.

The same goes for the belt portion 11B and the belt portion 5B. Similarly to the belt portion 11B, the belt portion 5B is divided into belt portions 5B₁ to 5B₄ that are connected with line portions 5D₁ to 5D₄, respectively. While the line portions 5D₁ to 5D₄ function as the word lines WL₅ to WL₈, respectively, the belt portions 5B₁ to 5B₄ function as pad portions HU₅ to HU₈ for the word lines WL₅ to WL₈, respectively.

Thereafter, in the present embodiment, an inter layer dielectric is formed on the whole surface of the substrate 1, contact holes that penetrate the inter layer dielectric and reach the pad portions HU₁ to HU₈ are formed, and contact plugs 21 are formed on the pad portions HU₁ to HU₈ in the contact holes. Furthermore, various interconnect layers, plug layers, inter layer dielectrics and the like are formed on the substrate 1. In this way, the semiconductor device of the present embodiment is manufactured.

FIG. 11 is a graph showing a relation of an initial space width between patterns of an upper layer and a final space width between patterns of a lower layer, when the patterns of the upper layer are transferred to the lower layer.

In the case where the initial space width is “Wa” or less, the final space width changes so as to be roughly proportional to the initial space width. For example, in the case where the initial space width is “Wa”, the final space width is “Wa′”, which is close to “Wa”. Therefore, in the case where the initial space width is “Wa” or less, the shape of the patterns of the lower layer is roughly equal to the shape of the patterns of the upper layer.

However, when the initial space width increases to a range of “Wa” to “Wb”, the change rate of the final space width decreases from a positive value to about 0, and further changes to a negative value. Further, in the case where the initial space width is “Wb” or more, the final space width is 0. Therefore, in the case where the initial space width is “Wb” or more, the patterns of the upper layer are not transferred to the lower layer.

Therefore, in the present embodiment, the space width between the line portions 17C₁, 17C₂ and the space widths between the line portions 18C₁ to 18C₄ are set to “Wa” or less. As a result, the patterns of the line portions 17C₁, 17C₂ are transferred to the first core material 14, as shown in FIGS. 5A and 5B. Furthermore, the patterns of the line portions 18C₁ to 18C₄ are transferred to the hard mask layer 13, as shown in FIGS. 8A and 8B.

Further, in the present embodiment, the space between the line portions 17C₁, 17C₂ in the +X direction from the dummy portions 17E and the space between the line portions 18C₁, 18C₄ in the +X direction from the connecting portion of the line portions 18C₂, 18C₃ are set to a width of “Wb” or more. As a result, the belt portion 14A is formed by the reverse loading effect, as shown in FIGS. 5A and 5B. Furthermore, the belt portion 13A is formed by the reverse loading effect, as shown in FIGS. 8A and 8B.

Further, in the present embodiment, the dummy portion 17E is formed between the line portion 17C₁ and the line portion 17C₂, and the dummy portions 18E₁, 18E₂ are formed between the line portions 18C₁, 18C₂ and the line portions 18C₃, 18C₄. As a result, a space remains between the belt portion 14A and the dummy portion 17E, as shown in FIGS. 5A and 5B. Furthermore, the opening portions R_(A1), R_(A2) remain at the corner portions of the belt portion 13A, as shown in FIGS. 8A and 8B.

Therefore, according to the present embodiment, by using the space and opening portions R_(A1), R_(A2), the trenches T_(A), T_(A1), T_(A2) are easily formed in the belt portion 11A, and the belt portion 11A is easily divided. In the present embodiment, the trenches T_(A), T_(A1), T_(A2) may be formed in the belt portion 11A, by using the above-described space and without using the opening portions R_(A1), R_(A2). An example of such a method will be explained in a modification of a second embodiment.

In the present embodiment, as shown in FIGS. 2A and 2B, the belt portion 15A is formed so as to surround the opening portion Q_(A). Therefore, according to the present embodiment, the dummy portion 17E can be formed between the line portion 17C₁ and the line portion 17C₂, and the space can remain between the belt portion 14A and the dummy portion 17E (FIGS. 5A and 5B). Further, according to the present embodiment, the dummy portions 18E₁, 18E₂ can be formed between the line portions 18C₁, 18C₂ and the line portions 18C₃, 18C₄, and the opening portions R_(A1), R_(A2) can remain at the corner portions of the belt portion 13A (FIGS. 8A and 8B).

Therefore, according to the present embodiment, it is possible to form the pad portions HU₁ to HU₄ from the belt portion 5A, simply and accurately. For example, it is possible to form a wide space in the ±X directions from the belt portion 11A (5A), and therefore, it is easy to avoid a mistaken cut of the word lines WL₁ to WL₄ by the trench T_(A). Further, it is possible to form the opening portions S_(A1), S_(A2) at the corner portions of the belt portion 11A (5A), and therefore, it is easy to avoid a mistaken cut of the word lines WL₁ to WL₄ by the trenches T_(A1), T_(A2).

Further, in the present embodiment, it is possible to form the belt portion 5A and the pad portions HU₁ to HU₄ in a nearly quadrangular shape. Therefore, according to the present embodiment, it is possible to set a wide area for the pad portions HU₁ to HU₄, and to enhance the integration degree of the semiconductor device.

Second Embodiment

FIGS. 12 and 13 are plan views showing a method of manufacturing a semiconductor device of a second embodiment.

FIGS. 12 and 13 correspond to FIGS. 9 and 10 respectively, and show the shapes of the control gate material 5 before division and after division. Belt portions HU_(A), HU_(B) in FIG. 12 represent the belt portions 5A, 5B, respectively.

As shown in FIG. 12, the word lines WL₁ to WL₄ are connected with a belt portion HU_(D), in addition to the belt portion HU_(A). Further, the belt portions HU_(A), HU_(D) are connected with word lines WL₁₃ to WL₁₆, also. The word lines WL₁₃ to WL₁₆, which are examples of the fifth to eighth interconnects respectively, are arranged so as to be adjacent to each other. Similarly to the first embodiment, dummy portions are arranged in the ±X directions from the belt portions HU_(A), HU_(D).

Similarly, the word lines WL₅ to WL₈ are connected with a belt portion HU_(C), in addition to the belt portion HU_(B). Further, the belt portions HU_(B), HU_(C) are connected with word lines WL₉ to WL₁₂, also. The word lines WL₉ to WL₁₂, which are examples of the fifth to eighth interconnects respectively, are arranged so as to be adjacent to each other. Similarly to the first embodiment, dummy portions are arranged in the ±X directions from the belt portions HU_(B), HU_(C).

As shown in FIG. 13, the belt portion HU_(A) is divided by the trenches T_(A), T_(A1), T_(A2), and the belt portion HU_(B) is divided by the trenches T_(B), T_(B1), T_(B2). This is the same as the first embodiment. Further, the word lines WL₉ to WL₁₆ are cut by a trench T_(E) that passes through the dummy portions in the +X directions from the belt portions HU_(A), HU_(B). As a result, the belt portions HU_(A), HU_(B) are separated (electrically insulated) from the word lines WL₉ to WL₁₆. Further, the belt portions HU_(A), HU_(B) are divided into pad portions HU₁ to HU₈ that are connected with the word lines WL₁ to WL₈, respectively.

Similarly, the belt portion HU_(C) is divided by trenches T_(C), T_(C2), and the belt portion HU_(D) is divided by trenches T_(D), T_(D1), T_(D2). Further, the word lines WL₁ to WL₈ are cut by a trench T_(F) that passes through the dummy portions in the −X directions from the belt portions HU_(C), HU_(D). As a result, the belt portions HU_(C), HU_(D) are separated (electrically insulated) from the word lines WL₁ to WL₈. Further, the belt portions HU_(C), HU_(D) are divided into pad portions HU₉ to HU₁₆ that are connected with the word lines WL₉ to WL₁₆, respectively.

The trenches T_(A), T_(B), T_(C), T_(D) may be formed by the cutting of the dummy portions as shown in the present embodiment, or may be formed without the cutting of the dummy portions as shown in the first embodiment.

FIG. 14 is a plan view showing a method of manufacturing a semiconductor device of a modification of the second embodiment.

FIG. 14 corresponds to FIG. 10, similarly to FIG. 13, and shows the shape of the control gate material 5 after division.

In FIG. 14, the trenches T_(A1), T_(A2) extend in the Y direction so as to link the trench T_(A) and the opening portions S_(A1), S_(A2), respectively, and the trenches T_(B1), T_(B2) extend in the Y direction so as to link the trench T_(B) and the opening portions S_(B1), S_(B2), respectively. Further, a trench T_(E1) extends in the Y direction such that the belt portions HU_(A), HU_(B) as well as the trenches T_(A), T_(B) are divided into four. Further, trenches T_(A3), T_(B3), T_(E2) are formed at the opening portions S_(A3), S_(A4), S_(B3), S_(B4) such that the word lines WL₉, WL₁₂, WL₁₃, WL₁₆ are cut.

As a result, the belt portions HU_(A), HU_(B) are separated (electrically insulated) from the word lines WL₂, WL₃, WL₆, WL₉, WL₁₂, WL₁₃, WL₁₆. Further, the belt portions HU_(A), HU_(B) are divided into the pad portions HU₁, HU₄, HU₅, HU₈, HU₁₀, HU₁₁, HU₁₄, HU₁₅ that are connected with the word lines WL₁, WL₄, WL₅, WL₈, WL₁₀, WL₁₁, WL₁₄, WL₁₅, respectively.

Similarly, the belt portions HU_(C), HU_(D) are separated (electrically insulated) from the word lines WL₁, WL₄, WL₅, WL₈, WL₁₀, WL₁₄, WL₁₅. Further, the belt portions HU_(C), HU_(D) are divided into the pad portions HU₂, HU₃, HU₆, HU₇, HU₉, HU₁₂, HU₁₃, HU₁₆ that are connected with the word lines WL₂, WL₃, WL₆, WL₇, WL₉, WL₁₂, WL₁₃, WL₁₆, respectively.

According to the present embodiment, similarly to the first embodiment, it is possible to form the pad portions HU₁ to HU₁₆ from the belt portions HU_(A) to HU_(D), simply and accurately.

The shape of the trench for dividing the belt portions HU_(A) to HU_(D) may be other than the shapes shown in FIG. 13 and FIG. 14. However, as for the trenches in FIG. 13, for example, the trenches T_(E), T_(F) for cutting the belt portions HU_(A) to HU_(D) and the word lines WL₁ to WL₁₆ have a line shape, and therefore, there is an advantage that the trenches T_(E), T_(F) are easily formed. Further, for example, the trenches in FIG. 14 have an advantage that the areas of the pad portions HU₁ to HU₁₆ are easily widened.

Third Embodiment

FIGS. 15 to 20 are plan views showing a method of manufacturing a semiconductor device of a third embodiment. In the description of the present embodiment, detailed descriptions for common matters with the first embodiment are omitted.

First, the gate insulator 2, the floating gate material 3, the inter gate insulator 4, the control gate material 5, the first mask layer 11, the second mask layer 12, the hard mask layer 13, the first core material 14, the second core material 15, and the resist film 16 are formed in order, on the substrate 1, and the resist film 16 is processed by lithography (see FIG. 1B).

[FIG. 15]

Next, by the etching using the resist film 16 as a mask, the second core material 15 is processed (FIG. 15). As a result, the second core material 15 is processed into a core material pattern including belt portions 15A, 15B, line portions 15C₁, 15C₂, 15D₁, 15D₂, and dummy portions 15E, 15F.

The belt portions 15A, 15B, which extend in the X direction, are examples of the first and second belt portions, respectively. The line portions 15C₁, 15D₁ extend mainly in the Y direction, and are connected with the belt portions 15A, 15B, respectively. The line portions 15C₁, 15D₁ are examples of the first and second line portions, respectively. The line portions 15C₂, 15D₂ extend mainly in the Y direction, and are connected with the belt portions 15A, 15B, respectively. The line portions 15C₂, 15D₂ are examples of the first and second line portions, respectively.

The dummy portion 15E is separated from the belt portions 15A, 15B and the line portions 15C₁, 15D₁, and has a line shape. In the present embodiment, there is a wide space U₁ between the belt portion 15A and line portion 15C₁ and the belt portion 15B and line portion 15D₁, and the dummy portion 15E is arranged in the space U₁.

The dummy portion 15F is separated from the belt portions 15A, 15B and the line portions 15C₂, 15D₂, and has a line shape. In the present embodiment, there is a wide space U₂ between the belt portion 15A and line portion 15C₂ and the belt portion 15B and line portion 15D₂, and the dummy portion 15F is arranged in the space U₂.

[FIG. 16]

Next, a first sidewall film 17 is formed on the side faces of the second core material 15, and the second core material 15 is removed by etching or ashing (FIG. 16).

The first sidewall film 17 includes line portions 17C₁ to 17C₄ formed on the side faces of the belt portion 15A and line portions 15C₁, 15C₂ of the second core material 15, and line portions 17D₁ to 17D₄ formed on the side faces of the belt portion 15B and line portions 15D₁, 15D₂ of the second core material 15.

The first sidewall film 17 further includes a dummy portion 17E formed on the side faces of the dummy portion 15E, and a dummy portion 17F formed on the side faces of the dummy portion 15F. The dummy portions 17E, 17F have a ring shape.

The line portions 17C₁, 17C₂ are connected with the line portions 17C₃, 17C₄, respectively, at the region where the belt portion 15A was present. Further, the line portions 17D₁, 17D₂ are connected with the line portions 17D₃, 17D₄, respectively, at the region where the belt portion 15B was present.

[FIG. 17]

Next, by the etching using the first sidewall film 17 as a mask, the first core material 14 is processed (FIG. 17). As a result, the first core material 14 is processed into a core material pattern including belt portions 14A, 14B, line portions 14C₁ to 14C₄, 14D₁ to 14D₄, and dummy portions 14E, 14F. The line portions 14C₁ to 14C₄, 14D₁ to 14D₄, and the dummy portions 14E, 14F, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the line portions 17C₁ to 17C₄, 17D₁ to 17D₄ and the dummy portions 17E, 17F.

The line portions 17C₁ to 17C₄, 17D₁ to 17D₄ and dummy portions 17E, 17F of the first sidewall film 17 are transferred to the first core material 14, and thereby, the line portions 14C₁ to 14C₄, 14D₁ to 14D₄ and dummy portions 14E, 14F in the present embodiment are formed.

On the other hand, the belt portions 14A, 14B in the present embodiment are formed by the reverse loading effect. However, the belt portion 14A is formed such that opening portions V_(A1), V_(A2) remain at end portions of the belt portion 14A. Further, the belt portion 14B is formed such that opening portions V_(B1), V_(B2) remain at end portions of the belt portion 14B. The reason is because the spaces at the end portions of the belt portions 14A, 14B are gradually widened, and therefore, the spaces near the end portions of the belt portions 14A, 14B are narrow.

[FIG. 18]

Next, a second sidewall film 18 is formed on the side faces of the first core material 14, and the first core material 14 is removed by etching or ashing (FIG. 18).

The second sidewall film 18 includes line portions 18C₁ to 18C₈ formed on the side faces of the belt portion 14A and line portions 14C₁ to 14C₄ of the first core material 14, and line portions 18D₁ to 18D₈ formed on the side faces of the belt portion 14B and line portions 14D₁ to 14D₄ of the first core material 14.

The second sidewall film 18 further includes dummy portions 18E₁, 18E₂ formed on the side faces of the dummy portion 14E, and dummy portions 18F₁, 18F₂ formed on the side faces of the dummy portion 14F. The dummy portions 18E₁, 18F₁ have a ring shape, and the dummy portions 18E₂, 18F₂ have a line shape.

The line portions 18C₁ to 18C₄ are connected with the line portions 18C₅ to 18C₈, respectively, at the region where the belt portion 14A was present. Further, the line portions 18D₁ to 18D₄ are connected with the line portions 18D₅ to 18D₈, respectively, at the region where the belt portion 14B was present.

[FIG. 19]

Next, by the etching using the second sidewall film 18 as a mask, the hard mask layer 13 is processed (FIG. 19). As a result, the hard mask layer 13 is processed into a hard mask pattern including belt portions 13A, 13B, line portions 13C₁ to 13C₈, 13D₁ to 13D₈, and dummy portions 13E₁, 13E₂, 13F₁, 13F₂. The line portions 13C₁ to 13C₈, 13D₁ to 13D₈ and the dummy portions 13E₁, 13E₂, 13F₁, 13F₂, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the line portions 18C₁ to 18C₈, 18D₁ to 18D₈ and the dummy portions 18E₁, 18E₂, 18F₁, 18F₂, respectively.

The line portions 18C₁ to 18C₈, 18D₁ to 18D₈ and dummy portions 18E₁, 18E₂, 18F₁, 18F₂ of the second sidewall film 18 are transferred to the hard mask layer 13, and thereby, the line portions 13C₁ to 13C₈, 13D₁ to 13D₈ and dummy portions 13E₁, 13E₂, 13F₁, 13F₂ in the present embodiment are formed.

On the other hand, the belt portions 13A, 13B in the present embodiment are formed by the reverse loading effect. However, the belt portion 13A is formed such that opening portions R_(A1) to R_(A4) remain at corner portions of the belt portion 13A. Further, the belt portion 13B is formed such that opening portions R_(B1) to R_(B4) remain at corner portions of the belt portion 13B. The reason is that the distance between the line portions 18C₁, 18C₂, the distance between the line portions 18D₁, 18D₂, and the like are short near the corner portions.

[FIG. 20]

Next, the second mask layer 12, the first mask layer 11, the control gate material 5, the inter gate insulator 4, the floating gate material 3 and the gate insulator 2 are processed by the etching using the hard mask layer 13 as a mask, and their belt portions are divided by lithography or etching (FIG. 20). As a result, the first mask layer 11 is processed into a mask pattern including belt portions 11A₁ to 11A₄, 11B₁ to 11B₄, line portions 11C₁ to 11C₈, 11D₁ to 11D₈, and dummy portions 11E₁, 11E₂, 11F₁, 11F₂.

The same goes for the control gate material 5, the inter gate insulator 4, the floating gate material 3, and the gate insulator 2. For example, the control gate material 5 is processed into an interconnect pattern including belt portions 5A₁ to 5A₄, 5B₁ to 5B₄, line portions 5C₁ to 5C₈, 5D₁ to 5D₈, and dummy portions 5E₁, 5E₂, 5F₁, 5F₂.

The belt portions 5A₁ to 5A₄, 5B₁ to 5B₄, the line portions 5C₁ to 5C₈, 5D₁ to 5D₈, and the dummy portions 5E₁, 5E₂, 5F₁, 5F₂, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the belt portions 11A₁ to 11A₄, 11B₁ to 11B₄, the line portions 11C₁ to 11C₈, 11D₁ to 11D₈, and the dummy portions 11E₁, 11E₂, 11F₁, 11F₂, respectively. The line portions 5C₁ to 5C₄, 5D₁ to 5D₄, 5D₈ to 5D₅, 5C₈ to 5C₅ function as word lines WL₁ to WL₁₆, respectively. Further, the belt portions 5A₁ to 5A₄, 5B₁ to 5B₄ function as pad portions HU₁ to HU_(B) for the word lines WL₁ to WL₈, respectively. The word lines WL₁ to WL₈ are examples of the first to eighth interconnects, respectively, and the dummy portions 5E₁, 5E₂ are examples of the one or more interconnects. Further, the belt portions 5A₁ to 5A₄ and belt portions 5B₁ to 5B₄ before division are examples of the first and second belt portions, respectively.

The belt portions 11A₁ to 11A₄ are connected with the line portions 11C₁ to 11C₄, respectively, and the belt portions 11B₁ to 11B₄ are connected with the line portions 11D₁ to 11D₄, respectively. The line portions 11C₁ to 11C₄, 11D₁ to 11D₄ extend mainly in the Y direction, and are arranged so as to be adjacent to each other. The line portions 11C₅ to 11C₈, 11D₅ to 11D₈ extend mainly in the Y direction, and are arranged so as to be adjacent to each other. The same goes for the belt portions 5A₁ to 5A₄, 5B₁ to 5B₄ and the line portions 5C₁ to 5C₈, 5D₁ to 5D₈.

The dummy portions 11E₁, 11E₂ are separated from the belt portions 11A₁ to 11A₄, 11B₁ to 11B₄ and the line portions 11C₁ to 11C₄, 11D₁ to 11D₄ and are positioned between the line portions 11C₁ to 11C₄ and the line portions 11D₁ to 11D₄. The dummy portion 11E₁ has a ring shape, and the dummy portion 11E₂ has a line shape. The same goes for the line portions 5C₁ to 5C₄, 5D₁ to 5D₄ and the dummy portions 5E₁, 5E₂. The dummy portions 5E₁, 5E₂ are separated (electrically insulated) from the belt portions 5A₁ to 5A₄, 5B₁ to 5B₄ and the line portions 5C₁ to 5C₄, 5D₁ to 5D₄.

The dummy portions 11F₁, 11F₂ are separated from the belt portions 11A₁ to 11A₄, 11B₁ to 11B₄ and the line portions 11C₅ to 11C₈, 11D₅ to 11D₈, and are positioned between the line portions 11C₅ to 11C₈ and the line portions 11D₅ to 11D₈. The dummy portion 11F₁ has a ring shape, and the dummy portion 11F₂ has a line shape. The same goes for the line portions 5C₅ to 5C₈, 5D₅ to 5D₈ and the dummy portions 5F₁, 5F₂. The dummy portions 5F₁, 5F₂ are separated (electrically insulated) from the belt portions 5A₁ to 5A₄, 5B₁ to 5B₄ and the line portions 5C₅ to 5C₈, 5D₅ to 5D₈.

Thereafter, in the present embodiment, an inter layer dielectric is formed on the whole surface of the substrate 1, contact holes that penetrate the inter layer dielectric and reach the pad portions HU₁ to HU₈ are formed, and contact plugs 21 are formed on the pad portions HU₁ to HU₈ in the contact holes. Furthermore, various interconnect layers, plug layers, inter layer dielectrics and the like are formed on the substrate 1. In this way, the semiconductor device of the present embodiment is manufactured.

In the present embodiment, as shown in FIG. 15, the wide space U₁ is present between the belt portion 15A and line portion 15C₁ and the belt portion 15B and line portion 15D₁. Furthermore, the wide space U₂ is present between the belt portion 15A and line portion 15C₂ and the belt portion 15B and line portion 15D₂. Therefore, when the pattern of the first sidewall film 17 is transferred to the first core material 14, there is a possibility that the first core material 14 remains under the spaces U₁, U₂ by the reverse loading effect.

Therefore, in the present embodiment, as shown in FIG. 15, the dummy portions 15E, 15F are arranged in the spaces U₁, U₂. Therefore, according to the present embodiment, it is possible to inhibit the first core material 14 from remaining under the spaces U₁, U₂ due to the reverse loading effect (FIG. 17). The same goes for the hard mask layer 13, the first mask layer 11, the control gate material 5 and the like (FIGS. 19 and 20). Therefore, according to the present embodiment, it is possible to prevent the short-circuit of the word lines WL₁ to WL₈ and the pad portions HU₁ to HU₈.

In the present embodiment, for preventing the above-described reverse loading effect, the distances between the dummy portions 15E, 15F and the other portion of the second core material 15 is set to “Wa” or less. The same goes for the dummy portions in the other layers.

As described so far, according to the present embodiment, it is possible to accurately form the pad portions HU₁ to HU₈, by the simple method in which the dummy portions 15E, 15F are arranged in the spaces U₁, U₂.

The structure and method of the present embodiment may be used in combination with the structure and method of the first embodiment or the second embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

1. A semiconductor device comprising: a substrate; first to fourth interconnects provided on the substrate so as to be adjacent to one another; a first pad portion connected with the first or second interconnect; a second pad portion adjacent to the first pad portion in a first direction; a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction perpendicular to the first direction; a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction; and one or more interconnects electrically insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.
 2. The device of claim 1, wherein the one or more interconnects include an interconnect having a ring shape.
 3. The device of claim 1, wherein the first and second pad portions are respectively connected with the first and second interconnects, and the third and fourth pad portions are respectively connected with the third and fourth interconnects.
 4. The device of claim 1, wherein the first and second pad portions are also adjacent to each other in the second direction, and the third and fourth pad portions are also adjacent to each other in the second direction.
 5. The device of claim 1, further comprising fifth to eighth interconnects provided on the substrate so as to be adjacent to one another, wherein the second pad portion is connected with the fifth or sixth interconnect, and the fourth pad portion is connected with the seventh or eighth interconnect.
 6. The device of claim 1, wherein the second pad portion is electrically insulated from the first and second interconnects, and the fourth pad portion is electrically insulated from the third and fourth interconnects.
 7. The device of claim 1, wherein a distance between an end portion of the first interconnect and an end portion of the second interconnect is greater than a space width between the first interconnect and the second interconnect.
 8. The device of claim 1, wherein a distance between an end portion of the third interconnect and an end portion of the fourth interconnect is greater than a space width between the third interconnect and the fourth interconnect.
 9. A semiconductor device comprising: a substrate; first to eighth interconnects provided on the substrate so as to be adjacent to one another; a first pad portion connected with the first or second interconnect; a second pad portion adjacent to the first pad portion in a first direction; a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction perpendicular to the first direction; a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction; a fifth pad portion connected with the fifth or sixth interconnect; a sixth pad portion adjacent to the fifth pad portion in the first direction; a seventh pad portion connected with the seventh or eighth interconnect, and adjacent to one of the fifth and sixth pad portions in the second direction; an eighth pad portion adjacent to the seventh pad portion in the first direction, and adjacent to the other of the fifth and sixth pad portions in the second direction; and one or more interconnects electrically insulated from the first to eighth interconnects and the first to eighth pad portions, and provided between the first to fourth interconnects and the fifth to eighth interconnects.
 10. The device of claim 9, wherein the one or more interconnects include an interconnect having a ring shape.
 11. A method of manufacturing a semiconductor device, comprising: sequentially forming an interconnect layer, a first film, a second film and a third film on a substrate; processing the third film into a first pattern including a line portion and a belt portion which is connected with the line portion and surrounds an opening portion; processing the second film into a second pattern using, as a mask, a first sidewall film formed on a side face of the first pattern; processing the first film into a third pattern using, as a mask, a second sidewall film formed on a side face of the second pattern; processing the interconnect layer, using the third pattern as a mask, into first to fourth interconnects, a belt portion connected with the first to fourth interconnects, and one or more interconnects separated from the first to fourth interconnects and the belt portion and positioned between the first and second interconnects and the third and fourth interconnects; and dividing the belt portion into a first pad portion connected with the first or second interconnect, a second pad portion adjacent to the first pad portion in a first direction, a third pad portion connected with the third or fourth interconnect and adjacent to one of the first and second pad portions in a second direction perpendicular to the first direction, a fourth pad portion adjacent to the third pad portion in the first direction and adjacent to the other of the first and second pad portions in the second direction.
 12. The method of claim 11, wherein the one or more interconnects include an interconnect having a ring shape.
 13. The method of claim 11, wherein the second pattern includes first and second line portions, a belt portion connected with the first and second line portions, and a portion separated from the first and second line portions and the belt portion and positioned between the first line portion and the second line portion.
 14. The method of claim 11, wherein the third pattern includes first to fourth line portions, a belt portion connected with the first to fourth line portions, and a portion separated from the first to fourth line portions and the belt portion and positioned between the first and second line portions and the third and fourth line portions.
 15. The method of claim 11, wherein a distance between an end portion of the first interconnect and an end portion of the second interconnect is greater than a space width between the first interconnect and the second interconnect.
 16. The method of claim 11, wherein a distance between an end portion of the third interconnect and an end portion of the fourth interconnect is greater than a space width between the third interconnect and the fourth interconnect.
 17. The method of claim 11, wherein the belt portion is divided such that the first and second pad portions are respectively connected with the first and second interconnects, and the third and fourth pad portions are respectively connected with the third and fourth interconnects.
 18. The method of claim 11, wherein the interconnect layer is further processed into fifth to eighth interconnects connected with the belt portion, and the belt portion is divided such that the second pad portion is connected with the fifth or sixth interconnect, and the fourth pad portion is connected with the seventh or eighth interconnect.
 19. A method of manufacturing a semiconductor device, comprising: sequentially forming an interconnect layer, a first film, a second film and a third film on a substrate; processing the third film into a first pattern including first and second line portions, first and second belt portions respectively connected with the first and second line portions, and a portion positioned between the first line portion and first belt portion and the second line portion and second belt portion; processing the second film into a second pattern using, as a mask, a first sidewall film formed on a side face of the first pattern; processing the first film into a third pattern using, as a mask, a second sidewall film formed on a side face of the second pattern; processing the interconnect layer, using the third pattern as a mask, into first to eighth interconnects, a first belt portion connected with the first to fourth interconnects, a second belt portion connected with the fifth to eighth interconnects, and one or more interconnects separated from the first to eighth interconnects and the first and second belt portions and positioned between the first to fourth interconnects and the fifth to eighth interconnects; dividing the first belt portion into a first pad portion connected with the first or second interconnect, a second pad portion adjacent to the first pad portion in a first direction, a third pad portion connected with the third or fourth interconnect and adjacent to one of the first and second interconnects in a second direction perpendicular to the first direction, and a fourth pad portion adjacent to the third pad portion in the first direction and adjacent to the other of the first and second interconnects in the second direction; and dividing the second belt portion into a fifth pad portion connected with the fifth or sixth interconnect, a sixth pad portion adjacent to the fifth pad portion in the first direction, a seventh pad portion connected with the seventh or eighth interconnect and adjacent to one of the fifth and sixth interconnects in the second direction, and an eighth pad portion adjacent to the seventh pad portion in the first direction and adjacent to the other of the fifth and sixth interconnects in the second direction.
 20. The method of claim 19, wherein the one or more interconnects include an interconnect having a ring shape. 